A bit-level pipelined VLSI architecture for the running order algorithm

Journal

IEEE Transactions on Signal Processing

Journal Volume

45

Journal Issue

8

Pages

2140-2144

Date Issued

1997

Author(s)

Chen, C.-T.

Chen, L.-G.

Hsiao, J.-H.

DOI

10.1109/78.611236

URI

http://www.scopus.com/inward/record.url?eid=2-s2.0-0031198689&partnerID=MN8TOARS

http://scholars.lib.ntu.edu.tw/handle/123456789/329305

Type

journal article