3-Dimensional Vertical Parallel Plate Capacitors in an SOI CMOS Technology for Integrated RF Circuits
Journal
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages
29-32
Date Issued
2003-06
Author(s)
Kim, Jonghae
Plouchart, Jean-Olivier
Zamdmer, Noah
Sherony, Melanie
Tan, Yue
Yoon, Meeyoung
Jenkins, Keith A.
Kumar, Mähender
Ray, Asit
Wagner, Lawrence
Abstract
This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 urn SOI CMOS technology. An effective capacitance density of 1.76 fF/μm2 is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.
Event(s)
2003 Symposium on VLSI Circuits
Subjects
CMOS; RF Circuits; SOI; VPP
Other Subjects
Capacitance; Capacitors; Electric resistance; Q factor measurement; Silicon on insulator technology; Skin effect; Radiofrequency (RF) integrated circuits; CMOS integrated circuits
Type
conference paper