With the growing demand on transmission rate, the serial data communication has evolved into tens of gigabits per second for wide area network (WAN) and the backbones. Synchronous Optical NETwork (SONET) and Synchronous Digital Hierarchy (SDH) have been developed to work at high transmission rates over optical fiber. High-speed circuits in multi-gigabits per second transceivers were mostly implemented in III-V technology or SiGe HBT. While CMOS process migrates into deep submicron technology, transceiver circuits of 10Gb/s OC-192 and 40Gb/s OC-768 on CMOS are achievable and becoming the mainstream for low cost, low power and high integration. Because of the characteristic of fiber, regenerators are essential for long-distance optical transmission. Hundreds to thousands of regeneration is possible within a SONET / SDH network, so stringent jitter transfer bandwidth and jitter peaking specifications pose great challenges on the design of a clock-and-data recovery (CDR) circuit for Optical Carrier (OC) system.
This thesis presents three chips for OC system. The first one is a half-rate voltage-controlled oscillator (VCO) for OC-192 system in 0.18µm 1P6M CMOS technology. Occupying an area of 0.66 × 0.95 mm2, 5GHz oscillation frequency with wide tuning range is achieved. It consumes a power of 6mW under 1.8V supply. The second chip is a half-rate VCO along with an injection-locked divide-by-two circuit for OC-768 system. Fabricated in 0.13µm 1P8M CMOS technology, an injection-locked frequency divider (ILFD) for 21.6GHz input is realized. The power consumption of ILFD is 4.8mW under 1.2V supply voltage. The final one is a CDR for OC-192 system. By applying a modified D flip-flop (DFF) and LC-tank VCO, a full-rate CDR is achieved in 0.18µm 1P6M CMOS technology. The chip occupies an area of 1.18 × 0.85 mm2 and consumes a power of 91mW under 1.8V supply. All the chips are verified from post-layout simulation and the former two are presented with measurement results.