VLSI Designs of LDPC Codec for IEEE 802.16e System

IEEE 802.16e standard, one of the advanced wireless communication systems as known as WiMAX, not only offers the static transmission, but also provides the limited mobility, especially for the applications of high data-rate transmission and voice communication at moving vehicles. In addition, it can cover larger transmission area, provide larger communication bandwidth and enhance bandwidth utilization. In order to increase transmission reliability, Low-density parity-check (LDPC) codes, which possess powerful error-correcting ability, become the important module of channel coding for IEEE 802.16e standard communication system.
LDPC codes were first introduced by Gallager in 1962 and were verified to possess superior properties in error-correcting field. Unfortunately, the past technology in 1960s wasn’t advanced enough to support their hardware implementation complexity. Therefore, LDPC codes weren’t widely discussed at that time and were left behind little by little. After three decades, it wasn’t an impossible mission to implement LDPC codes with the progress of the advanced VLSI technology. Therefore, the interests in LDPC codes were dramatically increased day by day.
The goal of the thesis is to give the delicate solutions for IEEE 802.16e standard communication system. At the aspect of encoders, the hardware realization can be implemented by the simple combinational circuits. On the other hand, an efficient design flow can be adopted with reordering of the base matrix, overlapped operations of key components and early termination strategy. The advantages are area reduction of die size, enhancement of hardware utilization, reduction of decoding latency, dynamic adjustment of decoding throughput and low power consumption.
In hardware implementation, our LDPC codec and multi-mode decoder design are both implemented in TSMC 0.13-um 1.2-V CMOS process with eight levels of metal. In our codec design, we can provide triple modes, including only encoding mode, only decoding mode and concurrent encoding and decoding mode. The die size is 2.88mm×2.88mm giving a total area of 8.29 mm2. In our multi-mode decoder design, we can provide 19 kinds of operating modes, including block sizes of 576, 672, …..., 2208, 2304. The die size is 2.91mm×2.91mm giving a total area of 8.47 mm2.