A 75-GHz PLL in 90-nm CMOS technology
Journal
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages
432-433+613+417
Date Issued
2007
Author(s)
Abstract
The design and experimental verification of a 75GHz PLL implemented in a 90nm CMOS process are presented. The circuit incorporates a three-quarter wavelength oscillator and a PFD based on SSB mixers and achieves an operation range of 320MHz and reference sidebands of less than -72dBc while consuming 88mW from a 1.45V supply.
SDGs
Type
conference paper