Design and Analysis of Power-Efficient ADCs
Date Issued
2006
Date
2006
Author(s)
Liao, Ying-Min
DOI
en-US
Abstract
By aggressive device scaling in modern integrated circuit technology, the computing power of digital circuits increases significantly. But the low power supply and relative high threshold voltage of transistors exhibit design constraints for analog circuit. Analog-to-digital converters provide the link between the analog world and the digital system. Due to their extensive use of analog and mixed analog-digital operations, A/D converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision.
For the increasing demand for portability and system-on-a-chip (SoC) integration, low-power dissipation and the compatibility with deep-submicron technology have emerged as important metrics in state-of-the-art ADC design. In SoC implementations, data converters are embedded on the same chip with powerful fine-line digital signal processing, resulting in a limited budget for their total heat and power consumption.
In this thesis, a 5-bit flash ADC was implemented by using capacitor-DAC array technique. The capacitor-DAC array provides efficient power strategy in conversion stage design. For the measurement results of the prototype fabricated in TSMC CMOS 0.18-μm 1P6M technology, the power dissipation is extremely low in 2-MHz sampling frequency. With the trend of increasing integration complexity of VLSI circuits, this design is capable of being adopted in the low-power 5-GHz wireless receiver system.
On the other hand, a 6-b high speed and low power pipelined successive-approximation ADC is presented. Employing improved-MMS and C-2C architecture, the circuit operates in high speed and low power consumption.. The proposed architecture reduces the static power consumption by charge redistribution digital-to-analog converter and lowers the accuracy requirement of the capacitor in the conventional SA-ADC by the C-2C architecture. Designed in a 0.18-μm technology, the ADC operates at 300-Ms/s clock rate while power dissipation is 252 mW.
Subjects
類比數位轉換器
導管化
漸進式
ADC
pipelined
successive-approximation
Type
thesis
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