The Investigation of Strained Si/Ge-Based MOS Devices and Charge Storage Memories

Strain technology is the most important technique in the current CMOS process, which can enhance the carrier mobilities in the channel region. On the other hand, the memory device is the most demanding driving force for the scaling. In the first part of the dissertation, we will investigate the strain effects on the physics and characteristics of the devices. For the rest part of the dissertation, the application and development of the new memory structure are studied (done at Professor T.P. Ma’s group at Yale University). We hope we can combine these two topics to enhance the device performance finally.
The Raman spectroscopy is often utilized to characterize the strain in the semiconductors. For Si, the red-shifts are observed under both the uniaxial and biaxial tensile strain. However, the unusual blue-shifts of the Ge Raman peak are observed at the specific laser polarization on (110) and (111) substrates. We use the lattice dynamical theory, secular equations, and the selection rules to repeat the above mentioned peculiar experimental results. The optimized phenomenological constants (p, q and r) are also proposed to fit the experimental data successfully.
Next, we investigate the flat-band voltage shifts of the metal-oxide-silicon capacitors fabricated on (001), (110), and (111) Si substrates under the external uniaxial and biaxial tensile strain. We demonstrate that the above mentioned phenomena are due to the movements of the conduction and valence band edges in the presence of the strain. The modulation of the work function of the metal gate electrode is only a minor contribution. We also fit the experimental data very well by the adequate deformation potential constants.
We have successfully grown the ultra thin with high Ge content Si0.8Ge0.2 layer directly on Si by UHVCVD. A nominal 3 nm Si cap layer was also grown on top of the Si0.2Ge0.8 layer to reduce the surface roughness and for passivation. On (001) substrate, there is ~3 x hole mobility enhancement for the Si/SiGe/Si quantum well PFET as compared with the bulk Si device for <110> channel.
The solid-state reaction of the Ni-Ge system is also studied. The resistivity of the NiGe phase is smaller than that of other Ni-germanide (Ni5Ge3, Ni2Ge) phases. By the powder XRD spectrum and TEM data, the Ni5Ge3 and Ni2Ge phases are observed on n-Ge (110) wafer at the room temperature and 600 ℃, causing the sheet resistance higher than the Ni/Ge samples on other orientation substrates at the same annealing temperatures. We have also used the Raman spectroscopy to characterize the strain induced by the germanide formation. Due to the larger lattice constant of the nickel-germanide, it will introduce the large tensile strain in the underlying Si substrate.
Later on, the material and electrical characteristics of the MOS capacitors using the p+ poly-InAs gate electrodes are discussed. The experimental result confirms that the 1 μm poly-InAs is thick enough to dominate the work function of the gate electrodes. The threshold voltage (Vth) of the Al/p+ poly-InAs gate devices has the positive modulation as compared to the control Al gate device. We expect that the large band gap of the III-V materials can compensate the undesired threshold voltage shifts by the high-k materials.
In the memory part (done at Professor T.P. Ma’s group at Yale University), the high quality, trap-less MAD Al2O3 is then used to replace the tunnel and blocking layer in the MONOS type flash memory because of the suppressed gate leakage current at the low electric field and enhanced tunneling current at the high electric field. The proposed MANAS stack is thus obtained with 4 V erase window can be achieved in 10 ms by using -14 V erase voltage. Besides, the 10-year projected retention window is as large as 2.5 V at 250 ℃.
Finally, we have also utilized the ferroelectric dielectrics to enhance the efficiency of the non-volatile memory. The property and function of the proposed ferroelectric dielectric has two parts. For the poly-crystalline portion, it is used to enhance the electric field of the tunnel layer. For the amorphous part, it is used as the charge storage layer. With this novel material, the huge memory window (~20 V) can thus be obtained. Furthermore, the stable charge retention characteristics also make this novel structure suitable for the multi-level charge storage.