nuKernel: MicroKernel for multi-core DSP SoCs with load sharing and priority interrupts
Journal
ACM Symposium on Applied Computing
Pages
1525-1532
Date Issued
2013
Author(s)
Shih, C.-S.
Abstract
The demands of modern embedded systems are hastening the adoption of multicore SoCs. Although multicore SoCs can be conceptually viewed as distributed systems, the resources on multicore SoCs including interrupts and scheduling are mostly, if not all, managed by the operating systems on general purpose CPU on SoC in a centralized manner. This approach leads to heavy overhead on the general purpose CPU and does not scale up. This paper presents the design and implementation of a microkernel for multi-core DSP SoCs, named nμKernel, to support real-time scheduling, load sharing among DSP cores, nested priority interrupts, and predictable interrupt latency jitter. The kernel takes advantage of both the shared memory architecture on multicore DSP SoCs and pipeline real-time scheduling to support load sharing. A server-base algorithm is designed for overrun control and to reduce load sharing overhead. The developed hybrid interrupt handling framework adopts on-demand interrupt thread mechanism to reduce interrupt handling overhead and support nested priority interrupts. The experiments show that the kernel can significantly enhance application performance with least management overhead. The frame rate of a secure image display application speeds up for six times: from 2.2 frames per second to 19 frames per second while workload are shared among DSP cores. The developed interrupt handling framework shortens the interrupted latency for up to 90%, compared to two-level interrupt handling mechanism and limits the range of interrupt latency to no more than 5%.
Type
conference paper