Design of CMOS Inductors and Their Applications for High-speed Front-end Circuits

As an introduction, some important fundamentals associated with on-chip inductors and front-end circuits have been introduced at first. In this dissertation, we proposed distributed capacitance model (DCM) to analyze parasitic capacitances in an on-chip inductor. Based on DCM, a simple and accurate approach to predict the behaviors of on-chip inductors is proposed. Experimental results show that the calculations of Cp and Csub without DCM much overestimate. The compact inductor model, which is built in accordance to the DCM, can be valid before the resonant frequency. The simple methodology not only provides a wide-band accurate inductor model but also saves inductor design time.
Enlighten from the propagation property of signal in an inductor, the methodology to calculate parasitic capacitance in differential symmetric inductors has been proposed, which has verified with differently-sized symmetric inductors. Moreover, a SMPS method has been proposed to move fQmax onto the desired frequency without additional processing steps. Utilizing the proposed SMPS technique, inductor’s fQmax can be moved onto circuit operating frequency to ameliorate circuit performance. Three 2.3-2.4GHz VCOs using planar, AMPS, and SMPS inductors, respectively, have also been implemented. The phase noise of the VCO using SMPS inductors can be improved by 9.3dB and 6dB at 100kHz offset frequency, compared to the VCOs using planar and AMPS inductors, respectively. The proposed SMPS technique can not only be applicable to VCO but also other RF circuitries.
Hereafter, we extend inductor design into our circuit applications. A bandwidth-extension technique called multiple inductive-series peaking technique. Two wide-band amplifiers: a 10Gb/s CMOS transimpedance amplifier and a CMOS bandpass VGA for an impulse-radio system have been reported to demonstrate the proposed technique. Employing multiple inductive-series peaking technique, the CMOS TIA reported here achieves gain of 61dBΩ with bandwidth of 7.2GHz. The CMOS VGA reported here can achieve 16dB peak power gain and the fractional bandwidth is 132% with tuning range of 20dB from 16dB to -4dB. The measured results demonstrate that the proposed technique of bandwidth extension can improve bandwidth performance significantly. The proposed technique of bandwidth extension is suitable for CMOS devices to achieve wideband and low-power characteristics simultaneously.
The other application, a novel QVCO with low phase-noise and low phase-error performances, has been presented. Employing parasitic vertical BJT and RC phase shifters, this work exhibits only 0.2∘phase error and phase noise of -103dBc/Hz at 100KHz offset frequency, which indicates FOM of 183. The tuning range is 380MHz with center frequency of 2.45GHz. The proposed QVCO is very suitable to direct-conversion transceivers for 2.4GHz wireless applications. And finally, we summarize this dissertation.