How to improve chip strength to avoid die cracking in a package
Resource
Thermal and Thermomechanical Phenomena in Electronic Systems, 2004. ITHERM '04. The Ninth Intersociety Conference on
Journal
Thermal and Thermomechanical Phenomena in Electronic Systems, 2004. ITHERM '04. The Ninth Intersociety Conference on
Pages
-
Date Issued
2004-06
Date
2004-06
Author(s)
Chen, Shoulung
Shih, I.G.
Chen, Y.N.
Tsai, C.Z.
Lin, J.W.
Wu, Enboa
DOI
N/A
Abstract
Die cracking is an annoying problem in the packaging industry. In our previous study, we have identified the weak region of the chip strength distribution in a wafer using the three-point bending test. It was found that the strength of the chips within the weak region was 30% to 50% lower than the averaged chip strength of the whole wafer, and the cause of the weak region was due to backside mechanical grinding. In this paper, additional thousands of chips on different wafers were tested to find the solution to enhance the chip strength in these weak regions, which included the effects of grinding speed, fine grinding depth, post processing using plasma etching or polishing, and search of optimal polishing depth. It was found from the experimental results that (a) slow down the grinding speed can increase chip strength in both the weak region and the whole wafer by approximately 50%, (b) although use of polishing after mechanical grinding increased the chip strength in the weak region, only 1 to 2 /spl mu/m thick polishing is considered adequate. On the other hand, use of coarse mechanical grinding only reduced the chip strength drastically to about 20% of the original value.
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Type
other
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