Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing scheme
Resource
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11 (4): 679-686
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
11
Journal Issue
4
Pages
679-686
Date Issued
2003
Date
2003
Author(s)
Abstract
Floorplanning/placement allocates a set of modules into a chip so that no two modules overlap and some specified objective is optimized. To facilitate floorplanning/placement, we need to develop an efficient and effective representation to model the geometric relationship among modules. In this paper, we present a P-admissible representation, called corner sequence (CS), for non-slicing floorplans. CS consists of two tuples that denote the packing sequence of modules and the corners to which the modules are placed. CS is very effective and simple for implementation. Also, it supports incremental update during packing. In particular, it induces a generic worst case linear-time packing scheme that can also be applied to other representations. Experimental results show that CS achieves very promising results for a set of commonly used MCNC benchmark circuits.
Subjects
Floor planning; Layout; Physical design; Placement; VLSI design
SDGs
Other Subjects
Graph theory; Mathematical models; Planning; Polynomials; Linear-time packing schemes; VLSI circuits
Type
journal article
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