This paper reports the unique
capacitance phenomenon of a 100nm
double-gate (DG) fully-depleted (FD) SOI
NMOS device with the n+/p+ poly
top/bottom gate. Based on the 2D
simulation result, the gate-drain/source
capacitance (CGD/CGS) of the device shows
a sudden fall at the gate voltage of 0.5V due
to the existence of the hole accumulation/
depletion in the bottom channel controlled
by the p+ bottom gate.
