Scalable Computation for Spatially Scalable Video Coding Using NVIDIA CUDA and Multi-core CPU
Date Issued
2009
Date
2009
Author(s)
Huang, Yen-Lin
Abstract
The scalable video coding (SVC), an extension of H.264/MPEG4-AVC, was standardized in 2007 by Joint Video Team (JVT) of the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group. SVC provides spatial, temporal and SNR scalabilities to serve multimedia systems or devices with various resolution, quality and computing power requirement. To achieve these three scalabilities, SVC uses additional coding tools and coding modes based on H.264/MPEG4-AVC, and most components of H.264/MPEG4-AVC are adopted in SVC design to allow the base layer of an SVC bit-stream can be decoded by any H.264/MPEG4-AVC compliant decoder. The coding tools used by SVC and the variety coding modes decision make the corresponding coding complexity become extremely high, so real-time realization of SVC is nearly impossible by using software and single-core CPU only. One possible solution to generate SVC streams in time is to parallelize the whole encoding process. Currently, multi-core CPU and GPU are two popular kinds of parallel processing architectures. Not much research has been devoted to realize the parallel SVC encoders based on the co-work of these two architectures. In this thesis, a scalable computation model for spatial SVC using multi-core CPU and GPGPU through NVIDIA CUDA is proposed. On the basis of the proposed computational model, a solution to solve the challenging data transition problem of this CPU-GPU co-work architecture is then provided. Simulation results show that, through our work, significant speed up gain in spatial SVC encoding can be achieved.
Subjects
Video coding
H.264/MPEG4-AVC
Scalable Video Coding (SVC)
GPU
Multi-core
CUDA
parallel computing
Type
thesis
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