Analysis of Capacitance Behavior in SOI CMOS Devices Using 2D and 3D Simulation
Date Issued
2005
Date
2005
Author(s)
Lin, Guei-Syuan
DOI
zh-TW
Abstract
In chapter 2, this thesis reports the three-dimensional analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3D fringing electric field effects. Based on the 3D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.1μm, the source sidewall fringing capacitance(CFSS) is the most important contribution to the gate-source capacitance (CGS) as compared to the inner oxide fringing capacitance (CFIS)and the drain side fringing capacitance (CFDS). For the gate-drain capacitance (CGD), the drain sidewall fringing capacitance (C’FDS) is the most important.
In chapter 3, this thesis reports the floating-body kink-effect related capacitance behavior of nanometer PD SOI NMOS devices. From the 2D simulation results, at the onset of the DC kink effect, there are sudden jumps in the CSG/CDG curves due to the excess holes stored in the thin-film as a result of the turn-on of the bipolar device.
In chapter 3, this thesis reports the floating-body kink-effect related capacitance behavior of nanometer PD SOI NMOS devices. From the 2D simulation results, at the onset of the DC kink effect, there are sudden jumps in the CSG/CDG curves due to the excess holes stored in the thin-film as a result of the turn-on of the bipolar device.
Subjects
絕緣體上矽
電容
三維
三度空間
突增
扭曲
浮動基體
窄通道
邊緣
SOI
Capacitance
3D
kink
PD
FD
floating body
CSG
CDG
CGS
CGD
mesa
narrow channel
fringing
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-94-R92943052-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):a0912c6dad3b13eead452689af8d8bfc