A precise delay generator circuit using the average delay technique
Journal
2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages
236-239
Date Issued
2008
Author(s)
Abstract
In this paper, a precise delay generator circuit using the average delay technique is realized in 0.18-mum CMOS 1P6M technology. The proposed delay generator achieves a high resolution and programmable delay by using the average delay technique. Compared with conventional delay generators, the proposed circuit achieves a higher resolution, uses less power, and has a smaller footprint. The input frequency is 400 MHz and the resolution is 25 ps.
SDGs
Type
conference paper