A 60-GHz 0.13-μm CMOS divide-by-three frequency divider
Journal
IEEE Transactions on Microwave Theory and Techniques
Journal Volume
56
Journal Issue
11
Pages
2409-2415
Date Issued
2008
Author(s)
Abstract
This paper presents the design and analysis of a 60-GHz 0.13-μm CMOS divide-by-three frequency divider (FD). The regenerative injection-locked technique is proposed to achieve divide-by-three function at millimeter-wave frequency. The novel level shifter is used to increase the overdrive voltage of the input switch of the loop divider such that the divider locking range and input sensitivity can be enhanced. The CMOS divide-by-three FD including the testing pads occupies the silicon area of 0.99 mm × 0.69 mm. Operated at 1.3 V, the CMOS divider consumes 13 mW of power. The measured locking range is 1.8 GHz around the input frequency of 59 GHz, and the phase noise of the output signal at 1-MHz offset is -131.36 dBc/Hz. © 2008 IEEE.
Subjects
60 GHz; CMOS; Divide-by-three; Frequency divider (FD); Millimeter wave
Other Subjects
Digital signal processing; Finite difference method; Frequency dividing circuits; Millimeter waves; Silicon; 1.8 ghz; 60 GHz; CMOS; Design and analyses; Divide-by-three; Frequency divider (FD); Frequency dividers; Input frequencies; Input sensitivities; Level shifters; Locking ranges; Millimeter-wave frequencies; Output signals; Overdrive voltages; Silicon areas; Voltage dividers
Type
journal article