Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications

The thesis describes the CHIP realization of 0.8v bulk CMOS DTMOS technique for optimization of low power system application. First, introduction on the low power, low voltage trends on CMOS SOC is described in chapter 1. Then a bulk PMOS DTMOS technique using MTCMOS and DTMOS technology is presented in chapter 2. Then the approach of chip realization in terms of integration of EDA tools for implementation an SOC chip using the bulk PMOS DTMOS technique is described. In chapter 3, detailed analysis of a test chip a 0.8v 16bit multiplier using the bulk PMOS DTMOS technique via the developed chip implementation technique using integrated EDA tools is described.