Energy Saving Based on CPU Voltage Scaling and Hardware Software Partitioning.
Journal
13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 17-19 December, 2007, Melbourne, Victoria, Australia
Pages
217-223
Date Issued
2007
Author(s)
Abstract
We examine the possible energy savings by mapping critical software functions from a microprocessor to configurable logics. A system-on-a-chip containing configurable logic is now commercially available. The configurable logic is typically intended to implement peripherals and co-processors without increasing chip count. We show that reduced software energy is an extra significant benefit, making such chips even more useful. We identify critical software functions of an application and implement them in the configurable logic such that the application can complete sooner, allowing us to put the system in a low-power state for longer periods, thus reducing energy. We use estimation-based approach for a hypothetical device having a 32-bit MlPS-extension processor plus on-chip configurable logic, yielding energy savings of 40%, increasing to 54% assuming voltage scaling.
SDGs
Type
conference paper