System Level Verification for Serial Advanced Technology Attachment Models

With the growth of CPU rate, the system performance depends on the speed of the system bus or the peripherals connected to it. Obviously, Parallel ATA is such a case and causes the loss of system performance. Thus, in order not to let such a situation exist, the best solution to storage interface is to replace the legacy Parallel ATA by the Serial ATA interface. Unfortunately, the traditional way to verify a design is time consuming since it's not applied from system point of view. As a result, system level verification and implementation become the main stream methodology and more and more significant nowadays.

In this thesis, I'll introduce a quick implementation methodology (using bus functional model, or so-called transaction verification model) to construct a set of system models for SATA and SATAII. Those models are
spec-oriented and can be viewed as virtual circuits since their behavior is just the same as the real circuits'. A SATA or SATAII interface is composed of four layers, which are physical layer, link layer, transport layer, and application layer respectively. With layered approach, throughput of SATA/SATAII interface can be further facilitated.

As mentioned above, verification from system point of view plays an important role when design is getting large. Hence, I'll provide several system verification techniques, such as transaction-based verification, assertion-based verification, coverage-based verification and so on, applied to either our BFMs or user's DUTs (device under test) for better functional coverage.