Camouflage circuit design and complementary lithography techniques with proximity effect correction for IC security
Journal
Proceedings of SPIE - The International Society for Optical Engineering
Journal Volume
13687
Start Page
80
ISSN
0277786X
ISBN (of the container)
978-151069320-3
Date Issued
2025-11-06
Author(s)
Editor(s)
Philipsen, Vicky
Melvin, Lawrence S.
Abstract
Counterfeit IC chips are an important issue in the modern electronics supply chain. Once the critical systems use counterfeit circuit parts, the reliability of the equipment will be affected. Therefore, counterfeit ICs are a matter of great concern to the electronics industry and governments worldwide, and many chip anti-counterfeiting technologies have been proposed. In recent years, inserting an electron beam (e-beam) maskless direct-write lithography into the standard CMOS process to write a unique read-only memory (ROM) chip ID for each chip has been demonstrated as a possible hardware anti-counterfeiting technology. However, the low speed is a weakness of e-beam lithography. It cannot wholly replace optical lithography in the high-volume manufacturing (HVM) of integrated circuits. The complementary lithography combines the optical and e-beam lithography to improve the throughput, where the e-beam lithography is used for the critical layers. This work proposes complementary lithography techniques for camouflage circuit designs in advanced technology nodes, integrating dummy contact-based camouflaging. The layouts of different logic cells differ only in the pattern of the via 0 layer, which is similar to the Via-programmable Gate Array (VPGA) design, where the via patterns determine the function of the logic circuit. Since the via 0 layer is located at the bottom of the Layout, it is difficult for hackers to distinguish the function of the logic circuit. The via 0 patterns of camouflage circuits will be simulated and analyzed through complementary lithography technology. EUV lithography is used to process the same parts in the via 0 patterns of different circuit layouts. The different parts in the via 0 patterns are customized with e-beam lithography. This work also extends the application of our previously proposed proximity effect correction approach to complementary lithography and applies it to the camouflage circuit designs. The effectiveness is evaluated in advanced processes.
Event(s)
Photomask Technology 2025
Subjects
Camouflage circuit design
complementary lithography
e-beam maskless direct-write lithography
EUV lithography
IC security
proximity effect correction
Publisher
SPIE
Type
conference paper