A flexible data-interlacing architecture for full-search block-matching algorithm
Resource
Application-Specific Systems, Architectures and Processors, 1997. Proceedings., IEEE International Conference on
Journal
IEEE International Conference on Application-Specific Systems, Architectures and Processors, 1997
Pages
-
Date Issued
1997-07
Date
1997-07
Author(s)
DOI
N/A
Abstract
This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on some cascading strategies, the same chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In addition, the cascading chips can efficiently reuse data to decrease external memory accesses and achieve a high throughput rate. Our results demonstrate that the architecture with 2-D data-reuse is a flexible, low-pin-counts, high-throughput, and cascadable solution for full search block-matching algorithm.
Type
journal article
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