Design of Through Silicon Via Assignments for Minimizing Simultaneous Switching Noise in 3D IC

Toward the design trends of high clock frequencies, high power density, low voltage levels, and small size for high-speed digital systems, the simultaneous switching noise (SSN) or ground bounce noise (GBN) in the circuits is becoming one of the major challenges for signal integrity (SI) and power integrity (PI).
This paper presents a design methodology to obtain the signal-ground or signal-ground-power through-silicon via (TSV) patterns in the on-chip power delivery network (PDN) with the minimized SSN using a genetic algorithm (GA). For the complex on-chip PDN, the equivalent impedance matrix method is used to calculate the equivalent inductance matrix for desired TSV patterns. The fast computational program to achieve the peak SSN analysis is developed with the simplified I/O buffer model. Based on the proposed methodology, the GA optimization for proper TSV pattern assignments with the various size and signal/ground/power ratios are shown and discussed.