The PI/SI Effects on Ultra High-Speed and Low Voltage SDRAM I/O Circuits with Decoupling Capacitors
Date Issued
2009
Date
2009
Author(s)
Lin, Yu-Hsiang
Abstract
This thesis presents a DDR4 I/O interface circuits operated at 1.1V and data rate is 3.2Gb/s. It is produced by standard UMC 90-nm CMOS process. In this chip, the transmitter and receiver circuits are included. To discuss the power integrity issue, we add many decoupling capacitors and transmitter circuits. In addition, we also consider transceiver’s eye-diagram and propagation delay time in different condition and discuss the signal integrity of this circuit.n this thesis, the variation of process, voltage and temperature with different model is discussed. It is included chip, chip with package and chip with package and board model which are simulated. And the result shows that although the performance is affected by the variation of process, voltage and temperature. But the effect by PVT is not more critical than we add the package and board model. Due to this reason, it is important to establish the package and board model in our simulation. Therefore, we also establish the board model which we measured and use it into our simulation. At the end, we compare with the result of our measurement and simulation.
Subjects
signal integrity
power integrity
Type
thesis
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