Structural-Optimization-Based Clock Network Synthesis
Date Issued
2012
Date
2012
Author(s)
Shih, Xin-Wei
Abstract
High-performance VLSI designs need small clock skew to maintain clocking speed. To minimize the skew, most earlier techniques optimized clock networks based on analytical timing models like the Elmore delay model. However, the literature shows that the accuracy of timing models might be insufficient to assist in achieving small skew for the high-performance designs. As a result, recent techniques embed simulations into the clock network synthesis to improve the accuracy. Nevertheless, the running time of the simulation-based synthesis would be prohibitively long. It is evident that using insufficiently accurate timing models and embedding time-consuming simulations might not minimize the skew effectively and efficiently. Therefore, we propose new structural optimization methods that minimize the skew by constructing a symmetrical structure. In the structure, configurations of all paths from the clock source to sinks are similar. Since the structural optimization requires neither timing models nor simulations, we can obtain small skew efficiently.
Moreover, in addition to the skew minimization, modern high-performance designs also bring critical challenges to the clock-network synthesis. Especially, the challenges of handling obstacles, IR-drops, and process variations are of particular importance. First, many designs introduce macros, which are obstacles for the clock network. A practical clock-synthesis approach must not fail with the presence of obstacles; otherwise, only a small number of designs without obstacles can adopt the approach. Second, power issues have high priority in high-performance designs. Since the clock network is a major device constantly triggered by the power network, a clock-synthesis approach should carefully consider effects on the power network, e.g., the IR-drop effect. Third, the process variations change the size of circuit elements (e.g., metal wires and poly gates) during chip fabrication. High-performance designs are highly sensitive to the process variations because even small changes could alter signal path timing and thus increase the skew drastically. Hence, it is desirable to enhance clock-network variation tolerance that maintains small skew when the process variations occur.
We propose several structural-optimization approaches to minimize the skew and to handle the three mentioned challenges. In this dissertation, our proposed approaches are detailed in four parts. (1) We present a symmetrical tree and corresponding synthesis algorithms to show the effectiveness of the skew minimization. (2) We design obstacle-avoiding mechanisms to show that the proposed symmetrical tree does not fail in the presence of obstacles. As avoiding obstacles may significantly lengthen routing wirelength, a weighted matching algorithm is also proposed to further minimize the wirelength. (3) Since the IR-drop effects change the supply voltages of clock buffers, we propose a voltage alignment algorithm to minimize the supply-voltage difference for the skew minimization. (4) To obtain good process variation tolerance, we develop two non-tree networks. A global-mesh network is proposed for providing the highest tolerance to variations, while a connected-mesh-island network is proposed to address the trade-off between the power consumption and the variation tolerance. According to the experimental results, our proposed structural optimization can effectively and efficiently minimize the clock skew, while most state-of-the-art works suffer from long running time due to the requirement of simulation.
Subjects
Physical Design
Clock
Clock Skew
Clock Power Consumption
Obstacle
IR-Drop
Buffer Supply Voltage
Process Variation
Type
thesis
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