Improving At-Speed Scan Test Quality by Hazard Elimination

As the IC manufacturing technology advances, at-speed testing becomes mandatory due to the shrinking timing budget and non-negligible process variations. However, high-quality at-speed testing is a challenging task due to the excessive circuit switching activity during test application.
In this thesis, we proposed a hazard elimination technique to improve at-speed testing quality. Hazards degrade at-speed test quality in the following manners. First, they cause excessive current consumption. The resulting abnormal IR-drop causes extra path delay and leads to yield loss. Second, unexpected hazards can speed up or slow down a signal transition to a much lager extent than IR-drop. The proposed hazard elimination technique effectively removes hazards that exhibit high impact on the target path. Robustly testable paths in s38417 are identified to validate the proposed technique. The average hazard reduction is 50 to 80%.