Design and Implementation of an Energy-Efficient Wide-Operating-Range SRAM
Date Issued
2013
Date
2013
Author(s)
Yang, Ya-Ting
Abstract
Embedded memories take an important place in today high-performance and low-power computing ICs. Along with the rapid growth of data requirement, memories can occupy the majority of the chip area and power consumption. This dominance forces designers to design high-density and low-power memories, which is the most effective way to reduce the overall power consumption of ICs. Static Random Access Memories (SRAM) have the advantage of high-speed and low-power operation, play an indispensable role in embedded memories.
In this thesis, we propose a 40nm wide-operating range SRAM, which can operate between 0.35v ~ 0.9v. The proposed SRAM can be operated at low voltage point to help reducing the power consumption and higher voltage range to meet the performance requirement. The SRAM’s power supply can be adjusted according to user’ needs. We use 8T SRAM cell with merged BLB/RBL as our memory cell and optimize the size to have a better stability in low-voltage range. In SRAM structure, we apply hierarchical BL/RBL to reduce the bit-lines’ loading and write/read access time. In peripheral circuit design, adaptive WL/RWL boosting skills are used to enhance the write and read ability. Adaptive low-swing RBL skill is also used to reduce the read access time and power. In order to tolerant process variation, dummy row/column timing control unit is applied to mimic the influence of global process variation, while extra WL/RWL boosting is applied to diminish the error probability cause by the local process variation. With the help of above techniques, we fabricate a wide-operating range, high-performance and energy-efficient 64Kb SRAM.
Subjects
靜態隨機存取記憶體
寬廣操作範圍
低電壓記憶體
低耗電
高效能
Type
thesis
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