Design and Analysis of Tens of Gb/s Multi-Channel Clock and Data Recovery Circuits
Date Issued
2014
Date
2014
Author(s)
Kao, Chien-Kai
Abstract
Wireline communication keeps exponential growth in recent years. To increase thethroughput of I/O connection, we can increase the data rata of I/O connection. However, the higher data rate may suffer from more channel loss. This increases the design difficulty on equalizer to compensate large high frequency loss. Besides, it is also a challenge for clock and data recovery to extract clock from a lossy data stream. Alternatively, we can increase the I/O counts to raise total throughput.
This thesis consists of two parts. The first part introduces architecture of a 4X16 Gb/s multi-channel clock and data recovery. We use phase-interpolator-based CDR and digital-controlled circuits to save chip area. And, a sub-harmonic injection-locked oscillator to generate low jitter quadrature clocks for phase interpolator. Then, jitter-tolerance enhancement technique is applied in our design. This circuit is implemented in 40-nm CMOS Technology.
The second part describes a 2X25 Gb/s two-channel clock and data recovery. To lower down power consumption of the system, charge-steering logic circuit is adopted in our design. An amplitude-locked loop (ALL) is proposed to suppress the output amplitude variation of charge-steering logic circuit. According to simulation results, this ALL can reduce 50% of output amplitude variation of CSL circuit. Meanwhile, the area and power overhead of ALL compared to the whole system are low. This circuit is implemented in 40-nm CMOS Technology.
Subjects
時脈資料回復電路
多通道
振幅鎖定迴路
Type
thesis
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