EFFP-NMC: An Energy-Efficient and Flexible Floating-Point Framework for Near-MRAM Computing
Journal
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Start Page
1
End Page
1
ISSN
2156-3357
2156-3365
Date Issued
2026-02-25
Author(s)
Liao, Chi-An
Abstract
Deep neural networks increasingly rely on floating-point (FP) formats to preserve accuracy and stability, but their integration with near-memory computing (NMC) faces significant energy efficiency challenges. MRAM offers low standby power and non-volatility for edge AI, yet suffers from high read-access energy, while FP workflows introduce costly alignment overhead. This work presents a flexible MRAM-based FP-NMC macro with three complementary innovations. Kernel-Wise Word-Line Mapping (KW-WLM) lowers access-activation complexity from O(N2) to O(N), achieving 10.1 − 2041× energy efficiency gain based on the image resolution, by maximizing weight reuse across pixels. Moreover, Delta-Exponent Aware Read (DEAR) introduces a lightweight control scheme that dynamically adjusts read granularity to exponent values, cutting redundant fetches and achieving 1.22 − 1.77× energy reduction. Finally, Multiple Reconfigurable Computing Schemes (MRCS) enable layer-wise precision reconfiguration, providing up to 1.14× energy efficiency gains while retaining near-software accuracy. These innovations mitigate MRAM’s access-energy bottlenecks and FP alignment overhead, enabling scalable, precision-flexible inference for real-world AI deployment.
Subjects
energy-efficient
floating-point (FP)
MRAM
near-memory computing (NMC)
neural network (NN)
reconfigurable architecture
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article