A low-cost architecture design with efficient data arrangement and memory configuration for MPEG-2 audio decoder
Resource
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Journal
IEEE International Symposium on Circuits and Systems, 1998. ISCAS '98
Pages
-
Date Issued
1998-06
Date
1998-06
Author(s)
DOI
N/A
Abstract
The paper describes a low-cost MPEG-2 audio decoder with a modified fast algorithm for decoding. In the modified decoding scheme, the computation amount of the bottleneck module can be reduced into one-forths of the original one. Also, the major memory storage only requires half size of the standard synthesis subband filterbank. The decoder is developed for the approaches of simplicity and low-cost architecture design, with the techniques of intelligent data arrangement and memory configuration.
Type
journal article
File(s)![Thumbnail Image]()
Loading...
Name
00698759.pdf
Size
273.04 KB
Format
Adobe PDF
Checksum
(MD5):fbb5c84df9554a31ee0f5894fa1e9ac0