High-Performance Reconfigurable Reed-Solomon Silicon IP Design for Communication/Storage Systems
Date Issued
2006
Date
2006
Author(s)
Hsu, Huai-Yi
DOI
en-US
Abstract
For high-performance reconfigurable Reed-Solomon Silicon IP design, this dissertation proposes various new techniques to design the VLSI architectures with both versatility and scalability. The proposed design techniques include multi-mode PGZ-based architecture, scalable modified Euclidean architecture, multi-symbols sliced PE-based architecture, and just-in-time folding ME architecture. They provide optimization to achieve the target of high performance in algorithmic, architecture, logic, and circuit levels. By using these techniques, this dissertation presents four design approaches, which are 1) a low-cost low-latency implementation for small t (t≦3) RS design (PGZ-RS IP), 2) a Reconfigurable RS codec for multi-standard / multi-mode communication/storage systems (RC-RS IP), 3) a power-aware dynamically reconfigurable RS design for portable device (MSS-RS IP), and 4) an area-efficient optical-rate RS design (OC-RS IP).
The PGZ-RS IP design can solve t=0, 1, 2, 3 errors in one unified VLSI architecture with very low hardware cost by using algorithm strength reduction method. The RC-RS IP design can easily be configured to serve the specified (n, k, t) value to perform multi-standard based on the scalable ME architecture for different systems. The MSS-RS IP design can provides power-aware feature to extend the battery life of portable devices. The OC-RS IP design can provide ultra high-speed performance for fiber systems by using the just-in-time folding ME architecture.
In summary, these four design examples presented in this dissertation demonstrate various design techniques which can be adopted in designing application-oriented reconfigurable Reed-Solomon Silicon IP.
Subjects
里德所羅門碼
可重規劃性
Reed-Solomon Code
Reconfigurable
Type
thesis
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