Hardware IP interface design and synthesis for System-on-a-Chip
Date Issued
2006
Date
2006
Author(s)
Lee, Ching-Hsin
DOI
en-US
Abstract
Hardware interface design is an elaborative step during intellectual property IP integration. Efficient System-on-a-Chip SoC design depends heavily on IP reuse and high level synthesis. As components of these two methods often have different communication interfaces with bus system, the design of their hardware interface is very time consuming. In this thesis, we propose a hardware interface design architecture which addresses portability, performance and verification. Our hardware interface architecture makes it possible to use data path direct-connection to increase performance. A detection technique is also presented to find out where the bottle neck of the data path is. An experimental result shows that data path direct-connection with bottleneck detection leads to up to 50% improvements in cycle counts. Our architecture also makes it possible to synthesize the hardware interface automatically. An automatic hardware interface synthesis tool is presented.
Subjects
匯流排
介面
數位矽智財
系統單晶片
bus
interface
Digital IP
IP
SoC
Type
thesis
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