Low Power Techniques for Phase-Locked Loops
Date Issued
2004
Date
2004
Author(s)
Chen, Yen-Wen
DOI
en-US
Abstract
The goal of this work is to use a standard 0.35-μm CMOS process to implement the phase-locked loops with low power consumption, and the new methods of these three topics, reducing the power consumption of the VCO and divider, reducing the switching power of the output buffer and a dividerless PLL, are presented.
The presented PLL include PFD, charge pump circuit, VCO, and divider, successfully reduces the power consumption on VCO and divider by regulated supply technique and novel schematic. To reduce the dynamic switching power consumption, we propose a new charge recycling buffer. The output transistors of the buffer will enter tri-state period first every time and do charge recycling in this period then the output starts transition.
A dividerless PLL can be implemented by Aperture Phase Detection (APD) technique because this method only compares reference and VCO phase ones every reference period. A proposed new APD cell can also reduce the jitter caused by the charge pump mismatch current.
Subjects
電源電壓調節
鎖相迴路
相位偵測器
低耗電
不需除頻器
輸出緩衝器
隙縫相位偵測
PFD
low power
PLL
dividerless
buffer
Aperture Phase Detection
regulated supply
Type
thesis
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