Design and Implementation of Delay-locked Loop Based Clock Generator
Date Issued
2011
Date
2011
Author(s)
Yu, Chien-Wei
Abstract
With the evolution and scaling down of CMOS technologies, the demand and applications for high-speed and high integration density wire-line communication system has recently grown exponentially. Hence, this thesis illustrates the implementation of the delay-locked loops (DLLs) based clock generator. Because of the operating frequency (or reference frequency) of wire-line communication system depends on the application. The range of operating frequency should be enlarged for more applications. However, the conventional phase-locked loops (PLLs) based frequency synthesizers are hard to optimize for wide reference range, and moreover, the issue of jitter accumulation and stability. Architecture and application about the proposed DLL-based clock generator are presented in order to solve problems that mentioned before.
Firstly, a DLL-based clock and data recovery (CDR) architecture implemented with 0.18-μm CMOS process is presented. Using the DLL for generate multi-phase signals. Then, synthesize the signal that multiplies the reference frequency by five. Furthermore, using the proposed half rate phase detector (PD), the speed on controlled-line can be lowered; the error and loading can be improved. The test circuit and building block circuit design are illustrated, and the measurement results are also described.
In the second work, a DLL-based frequency multiplier with anti-harmonic locking technique is proposed. With the anti-harmonic PD, when the operating frequency changing the PD can lock correctly in continues time. Moreover, the single-ended delay cell and transition detector can prevent the error by duty cycle distortion. Implemented with standard TSMC 0.18-μm CMOS process, a DLL-based frequency multiplier is proposed and the measurement results are also demonstrated.
Subjects
Delay-locked loop
Frequency multiplier
Anti-harmonic locking phase detector
Type
thesis
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