A wide-range and fast-locking clock synthesizer IP based on delay-locked loop
Journal
IEEE International Symposium on Circuits and Systems
Journal Volume
1
Date Issued
2004
Author(s)
Abstract
A wide-range and fast-locking clock synthesizer IP based on delay-locked loop is proposed. The ROSC-type cyclic delay line is employed for clock generation. A frequency detector is designed to provide fast-locking capability and the frequency switching behavior like the traditional PLL-based clock synthesizer. This design also includes initial start-up circuitry to activate the whole system from unlimited delay. The proposed clock synthesizer can solve the problem of changing frequency comparing to the conventional DLL-based clock synthesizers. Simulation results show that the output frequency range can operate from 10 to 500 MHz. the HSPICE simulation results are based upon TSMC 0.35/spl mu/m 2P4M CMOS process with a 3.3V power supply voltage. The power is less than 30mW at the highest output frequency. The core area for the design is 0.095mm/sup 2/.
SDGs
Type
conference paper