The Sea-of-Wires Array Aynthesis System.
Journal
Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993.
Pages
188-193
Date Issued
1993
Author(s)
Abstract
The primary intent of this research has been to develop a complete VLSI synthesis system targeting on a unique CMOS design capability, which is derived from a methodology known as Sea-of-Wires Arrays (SWA). The new capability is expected to yield the performance benefits of a custom design while maintaining the quick turnaround and ease of semicustom design for ASIC applications. The research begins by showing that the SWA architecture based on distributed gates is a promising approach to VLSI design. The synthesis and optimization algorithms form the core of the design system whose goal is high-performance SWA design. The innovative table lookup timing analysis approach facilities a fast and accurate performance evaluation. The effectiveness of the SWA design methodology is finally assessed by evaluations of AHPL Benchmarks with respect to area required and resource utilization.
Type
conference paper