The extraction of inductors and capacitors from layout of microwave multi-layer circuits
Date Issued
2007
Date
2007
Author(s)
Chang, Yung-Shuen
DOI
en-US
Abstract
There are two parts in this thesis. The first part is about the component extraction, and this part applies a lot of computation geometry algorithms. We use computational geometry to design an algorithm to recognize components. Circuit components extracted include capacitors, inductors, forks and vias. The second part is about netlist generation. In this part, we designed an algorithm to link up all information of polygon effectively. The sub-netlist can be extracted by extracting the point information and the edge relation of polygons, and generate the full netlist. The two parts are the front-end of layout vs. schematic check (LVS).
Subjects
電容
電感
萃取
佈局對電路圖檢查
計算機幾何
capacitor
inductor
extraction
layout vs. schematic check
LVS
computational geometry
Type
thesis
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