Embedded JPEG encoder IP core and memory efficient preprocessing architecture for scanner
Journal
IEEE Asia-Pacific Conference on Circuits and Systems
Pages
686-689
Date Issued
2000
Author(s)
Abstract
In this paper a baseline JPEG encoder soft intellectual property (IP) is proposed together with a memory efficient preprocessing architecture for scanner to solve the bandwidth problem between PC and scanner. This JPEG IP features quantization tables that are reconfigurable at run time and compile time. It is a modularized and fully pipelined design with friendly interface, which makes it easier to be integrated into various application systems. It is silicon proven to run up to 40 MHz at 3.3 V. With the optimized preprocessing unit feeding data smoothly into JPEG core, it is a low cost and competitive solution for a scanner to have a compression function embedded.
SDGs
Type
conference paper