Sleep Transistor-Aware Modified Composite Current Source Model
Date Issued
2009
Date
2009
Author(s)
Pai, Shang-Chien
Abstract
As the semiconductor technology advances, feature sizes continue to shrink. No-wadays 45nm technology and even 32nm technology have been largely employed in the design of modern Integrated Circuit Design. However with the advancement of shrink-ing feature sizes, comes the problem of leakage current. As the gate oxide thickness be-coming thinner with the advancing technology, this problem can no longer be ignored. The newest research results demonstrate that the leakage power accounts for 42% of total power and thus must be reduced for the design of VLSI circuits.leep transistor is a vastly used technique for reducing leakage power. The theory behind it is to simply cut off the gates that are not in use to further reduce the leakage power. However the traditional Current Source Models for Static Timing Analysis have no consideration for the effect of the addition of a sleep transistor. This limits the design ability of circuits with sleep transistors and introduces uncertainties in the design.n this thesis, we proposed a Modified Composite Current Source Model to not only model the output of standard gates but to model the effect of a non-stable ground. In addition this model demonstrates the ability of persevering the output waveform from stage to stage. There is no need of recalculating an input transition value after ever stage. Experimental results compared with HSPICE results show an average delay error of less than 2%.
Subjects
VLSI
Leakage Power
Sleep Transistor
Current Source Models
Static Timing Analysis
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-98-R95943170-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):f2dd264f6e7d3c6b37b24904af7fabee