A memory management unit and cache controller for the MARS system
Journal
Proceedings of the Annual International Symposium on Microarchitecture, MICRO
Pages
200-208
Date Issued
1990
Author(s)
Abstract
For large caches, the interaction between cache access and address translation affects the machine cycle time and the access time to memory. The physically addressed caches slow down the cache access due to the virtual address translation. The virtually addressed caches is faster, but the synonym problem is difficult to handle. By some software constraints and hardware support, our virtually addressed physically tagged caches can achieve the same speed as traditional virtually addressed cache and solve the synonym problem. The design of delayed miss signal makes the TLB access depart from the critical path of the cache access. A simple method to solve the TLB coherence is implemented in this chip and only a little hardware is required. © 1990 IEEE Computer Society. All rights reserved.
Other Subjects
Hardware; Memory management units; Microprogramming; Physical addresses; Semantics; Virtual addresses; Address translation; Cache access; Cache controller; Critical Paths; Hardware supports; Large caches; Machine cycle; SIMPLE method; Cache memory
Type
conference paper