An Energy-Efficient Resilient Flip-Flop Circuit with Built-In Timing-Error Detection and Correction
Journal
IEEE VLSI-DAT
Date Issued
2015-04
Author(s)
Abstract
This paper presents a timing error resilient flip-flop (ERFF) circuit with high energy-efficiency. The proposed flip-flop design automatically corrects timing errors and therefore minimizes the performance degradation due to variations. The simulation results show that the proposed design can achieve better energy-efficiency in ISCAS'89 benchmark circuits and LEON3 integer-processing unit, when compared to other state-of-the-art timing error detection and correction methods. © 2015 IEEE.
Subjects
DVFS; energy efficient; flip-flop; timing error detection and correction; wide-operating voltage processor
SDGs
Other Subjects
Energy efficiency; Error detection; Timing circuits; VLSI circuits; Benchmark circuit; DVFS; Energy efficient; Flip-flop designs; High energy efficiency; Operating voltage; Performance degradation; Timing error detection; Flip flop circuits
Type
conference paper