A digital calibration technique for charge pumps in phase-locked systems
Journal
IEEE Journal of Solid-State Circuits
Journal Volume
43
Journal Issue
2
Pages
390-398
Date Issued
2008-02
Author(s)
Abstract
A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked systems. In this digital calibration technique, there is no extra replica CP needed. In addition, it can calibrate the CP under different control voltages on the loop filter to be immune to the channel-length modulation. Due to the digital nature, the additional power consumption and digital switching noise from the calibration circuits are turned off once the calibration is finished. A 5 GHz frequency synthesizer is used to justify the proposed calibration technique. The measured output spur is suppressed by 5.35 dB at 5.2 GHz after the calibration circuits are active. The measured output spur levels are less than -68.5 dBc throughout the whole output frequency range. The measured phase noise is -110 dBc/Hz at an offset frequency of 1 MHz. © 2008 IEEE.
Subjects
Charge pump (CP) calibration; Digital calibration; Frequency synthesizer; Phase-locked loop (PLL)
SDGs
Other Subjects
Electric potential; Frequency synthesizers; Natural frequencies; Switching; Channel length modulation; Charge pump (CP) calibration; Control voltages; Digital calibration; Phase locked loops
Type
journal article