A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
Resource
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Journal
IEEE International Symposium on Circuits and Systems
Pages
4082-4085
Date Issued
2006-05
Date
2006-05
Author(s)
DOI
N/A
Abstract
This paper presents a frequency-estimation algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and synchronization process, the lock time can be optimized to two cycles. As the reference clock varies or frequency multiplication switches, lock time holds in two reference clock cycles. An implementation of proposed ADPLL design is realized in UMC 0.18 mum 1P6M CMOS technology with core area of 520times530 mum 2 . The PLL has the frequency range of 140 MHz to 1030 MHz with 22ps DCO resolution
Type
conference paper
File(s)![Thumbnail Image]()
Loading...
Name
01693526.pdf
Size
3.06 MB
Format
Adobe PDF
Checksum
(MD5):8a56a1ee45664542bae1d5f140fb5720