A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time

Resource

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Journal

IEEE International Symposium on Circuits and Systems

Pages

4082-4085

Date Issued

2006-05

Date

2006-05

Author(s)

Wu, Chia-Tsun

Wang, Wei

Wey, I-Chyn

DOI

DOI

N/A

URI

Type

conference paper

File(s)

Name

01693526.pdf

Size

3.06 MB

Format

Adobe PDF

Checksum

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