A digitally-calibrated phase-locked loop with supply sensitivity suppression
Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal Volume
19
Journal Issue
4
Pages
592-602
Date Issued
2011-04
Author(s)
Shih-Yuan Kao
Abstract
A digitally-calibrated technique to suppress the supply voltage sensitivity of a phase-locked loop (PLL) is presented. The voltage-controlled ring oscillator with an additional opposite-supply-sensitivity pair is digitally calibrated to suppress the supply voltage sensitivity. The circuit is fabricated in a 0.18-m CMOS technology and the core area occupies 0.235 mm 2 . The total power consumption is 16.2 mW for a supply voltage of 1.8 V and an operating frequency of 1.5 GHz. For a 100 mV pp , 110 kHz sinusoidal waveform noise applied to the supply, the measured rms jitters without and with calibration are 16.5 and 9.7 ps, respectively, while this PLL works at 1.5 GHz. This PLL achieves the rms jitter improvement by a factor of 41.2% under the proposed digitally-calibrated technique.
SDGs
Type
journal article