Effect of Gate Metal Thickness on The 2-State Characteristics of MOS Structure with Ultrathin Oxide
Date Issued
2015
Date
2015
Author(s)
Tan, Yu-De
Abstract
In this work, we study the effect of the thickness of gate metal on the characteristics of Metal-Oxide-Semiconductor capacitor (MOSCAP) device with ultrathin oxide layer. The embedded Dynamic Random Access Memory (eDRAM) becomes more and more important in semiconductor industry with application of System on Chip (SoC) and Application Specific Integrated Circuit (ASIC). The pattern of the device is a long strap connected to a square contact pad in this work, which is designed for higher gate resistance with ultrathin gate metal. The device has two operation modes, i.e., current mode and capacitance mode. For current mode operation, the device exhibits 2-state characteristic with opposite readout current sign, which we define as ‘1’-state and ‘-1’-state. The device has retention time constant of about 210ms, which matches the specification of ITRS. And it has endurance of at last one million cycle of write operation. For capacitance mode operation, the device shows CV hysteresis with thinner gate metal and thin oxide layer. The level of CV hysteresis is sensitive to sweeping range and stress holding time. And the two factors are tradeoff for high sensitivity. The capacitance 2-state characteristic of the MOSCAP device has the potential to evolve into transistor memory. The device discussed in this work has advantage of simple structure, smaller feature size, CMOS process compatible, and low operation power consumption.
Subjects
MOS devices
DRAM
embedded DRAM
ultrathin oxide
ultrathin gate metal
2-state characteristic of current, 2-state characteristic of capacitance
Type
thesis
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