A low power 2D DCT chip design using direct 2D algorithm
Resource
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Journal
Design Automation Conference 1998
Pages
Proceeding-s
Date Issued
1998-02
Date
1998-02
Author(s)
DOI
N/A
Abstract
In this paper, a low power 8/spl times/8 2D DCT architecture based on direct 2D approach is proposed. The direct 2D consideration reduces computational complexity. According to this algorithm, a parallel distributed arithmetic (DA) architecture at reduced supply voltage is derived. In the real circuit implementation of the chip, a hybrid-architecture adder of low power consumption is designed, as well as a power-saving ROM and a low voltage two-port SRAM with sequential access. The resultant 2D DCT chip is realized by 0.6 /spl mu/m single-poly double-metal technology. Critical path simulation indicates a maximum input rate of 133 MHz, and it consumes 138 mW at 100 MHz.
SDGs
Type
journal article
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