VLSI Design Techniques of LDPC Codec for Enhanced Throughput and Efficiency
Date Issued
2007
Date
2007
Author(s)
Zhan, Cheng-Zhou
DOI
zh-TW
Abstract
In modern communication systems, the low-density parity-check (LDPC) codes are adopted in several ones, such as IEEE 802.16e (mobile WiMAX), IEEE 802.11n, and 10GBase-T system. The demand for speed of the channel decoder grows from the tens of Mbps of IEEE 802.16e standard, hundreds of Mbps of IEEE 802.11n standard, to 10 Gbps of 10GBase-T system. This indicates that the need for the speed of the channel decoder is growing rapidly. To increase the reliability of the transmission, LDPC codes have become an important channel-decoding module in the communication systems.
LDPC codes are first discovered by Dr. Galleger in 1962, and are proved to have great abilities for channel decoding. The technology in 1962 was not advanced enough to support these complex designs of LDPC codes, and it was rediscovered in the late 19 century.
The goal of this thesis is to propose several techniques to improve the throughput, hardware utilization efficiency (HUE), and an early termination scheme to reduce the decoding latency. In hardware implementation, we will construct a simplified LDPC encoder suitable for the IEEE 802.11n standard, and construct the LDPC decoder by using the techniques mentioned in this thesis to prove the feasibility of our algorithms and techniques.
We use the 0.13 technology of the cell-based design flow to implement our LDPC-codec chip suitable for single-mode IEEE 802.11n standard, and the chip area is 2.65mm×2.65mm.
Subjects
低密度
吞吐量
奇偶校驗碼
效率
無線通訊
LDPC
throughput
efficiency
IEEE 802.11n
wireless
Type
thesis
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