An 8Gb/s Clock and Data Recovery Using Eye-Opening Monitor Technique
Date Issued
2011
Date
2011
Author(s)
Hung, Hui-Wen
Abstract
Traditional CDR circuits can be categorized as PLL-based CDR and oversampling CDR based on its architecture. The sampling position of these CDR circuits is always fixed in the middle of the received data. However, when data is transmitted in channel, it is distorted by some non-ideal factors such as noise, ISI and timing jitter. Therefore, the best sampling position is not at the middle of the received data by BER analysis. In order to apply in different channel conditions and reduce the complexity of the front equalizer, an eye-opening monitor (EOM) CDR circuit is proposed based on the oversampling architecture. In different channel conditions, the EOM CDR circuit can select one clock phase to recover data at the position where has low BER. Furthermore, the EOM is turned off after having selected the most appropriate sampling clock to save the power consumption of CDR circuit.
This EOM CDR circuit is implemented with 90nm CMOS technology, and the core is occupied an area of 0.7mm∗0.8mm. Moreover, this circuit consumes 254mW from 1.0V supply when the EOM turns on, and only costs 61mW after having selected one appropriate sampling clock. Without any pre-equalizer or pre-emphasis circuit, this proposed EOM CDR circuit can recover the 8Gb/s data, which is passing through 30cm FR-4 channel with BER < 10^(−12).
Subjects
high-speed serial link system
clock and data recovery
eye-opening monitor
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