Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
Date Issued
2015
Date
2015
Author(s)
Chiang, Kuan-Ying
Abstract
FinFET has become the most popular solution to overcome short channel effects in advanced technology. However, some research show that defect in FinFET causes extra small delay and the defect is difficult to detect by traditional test sets. Sometimes, defect in FinFET circuits may affect multiple gates due to fabrication process. We named it a cross-gate defect. By accumulating the extra delay induced by the cross-gate defect, we can detect the small delay defect more easily. In this thesis, we proposed a FAST fault model for small delay faults induced by cross-gate defects in FinFET circuits. This fault model is especially designed for fins open cross-gate defect. FAST ATPG, fault simulation, and test pattern selection are also presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL than those of commercial tool timing-unaware 1-detect pattern sets.
Subjects
FinFET
SDD
ATPG
fault simulation
Type
thesis