Algorithm and Architecture Design of Prediction Core for Stereo Video Coding Systems
Date Issued
2005
Date
2005
Author(s)
Ding, Li-Fu
DOI
en-US
Abstract
Stereo video can make users sense depth perception by showing two frames to each eye simultaneously. It can give users a vivid information about the scene structure. With the technology of 3D-TV getting more and more mature, stereo and multi-view video coding draw more and more attention. However, to build up a stereo video coding system, many design challenges, such as bad coding efficiency and high computational complexity, must be overcome.
In this thesis, the algorithm and the architecture design of the prediction core for stereo video systems are proposed. In algorithm level, the proposed joint prediction scheme is composed of three coding tools. They are joint block compensation, MV (motion vector) -DV (disparity vector) prediction, and mode pre-decision. Joint block compensation utilizes the weighted sum of motion- and disparity-compensated blocks, which can make our system outperform MPEG-4 Temporal Scalability and Simple Profile by 2–3 dB in rate-distortion performance. On the other hand, MV-DV prediction, which utilizes the correlation between MVs and DVs, and mode pre-decision which utilizes the characteristics of stereo video, successfully reduce about 80% computational complexity.
Besides, in architecture level, a hardwired prediction core architecture design is proposed to provide a cost-effective solution to prediction core implementation in stereo video systems. Proposed scheduling saves 23% on-chip SRAM, and new algorithm for bandwidth reduction successfully reduces 35% data access bandwidth. Compared with the hardware requirement for the prediction core with full search block matching algorithm (FSBMA), only 11.5% of on-chip SRAM and 1/30 amount of processing elements (PEs) are needed. It shows that it is an efficient architecture design. The prototype chip can achieve real-time requirement under the operating frequency of 81 MHz for 30 D1 frames per second (fps) in the left and the right channel simultaneously, with ME (motion estimation)/DE (disparity estimation) search range of [-64, +63] in horizontal direction and [-32, +31]/[-16, +15] in vertical direction. The prototype chip is fabricated by TSMC 0.18 µm 1P6M CMOS process via CIC. The chip size is 2.77895 × 2.77895 mm2. Two-input NAND gate coun is 137K, and only 22.75K bits SRAM are used for such high specifications. Besides, It is the first prediction core chip designed for stereo video coding systems in the world.
Moreover, in system integration level, a prototype of real-time stereo video system is successfully built up. The system integrates a stereo video camera, FPGA accelerator, software optimization, network transmission, and 3D display LCD. The demonstration results prove the proposed algorithm and architecture of the prediction core indeed improve the performance of stereo video coding systems.
Subjects
立體視訊編碼
移動估計
位移估計
stereo vdieo coding
disparity
disparity estimation
Type
thesis
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