Strain Analysis of Through Silicon Vias (TSVs) and FinFET Stressors
Date Issued
2012
Date
2012
Author(s)
Yeh, Che-Yu
Abstract
The numbers of transistor in the circuit and performance may be double every eighteen months. To follow Moore’s law, we scaled down the transistor in the past,but the lithography technology beyond 22nm node may suffer from bottleneck. There are some technologies to solve this problem, one is three dimension structure likes FinFET, and another is three dimension package likes TSVs.
The via may be filled with metal to connect the signal. Because of the large difference of coefficient of thermal expansion between metal and semiconductor, it will lead to strain field as the process temperature is cooling down to room temperature. The strain may change the uniformity or deform the device. In this thesis, we will calculate the strain field induced by TSVs and check the effect to surrounding device. At first, we use two dimensions model to define the keep-out zone and we find the circular pattern can put more transistors because it will decrease the keep-out zone. To compare with the real situation, we derive the
analytic solution in three dimensions by the Kane-Mindlin theory. Our model is fit for the middle plane of wafer and the device will often locate in the surface of wafer, so we need to revise it by correction factor. We find the result is similar between numeric solution and analytic solution. Besides, we use the superposition theory to fit the strain field of multiple TSVs, we get the similar result by corrections. At last,we further compare isotropic material of analytic solution with orthotropic material of numeric solution. We can still get the similar result by corrections.
The strain technology used in the 90 nm node can still be well suited to the three dimensions transistor. The other part of this thesis will introduce the strain analysis
of FinFET stressor. Firstly, we study the strain analytic solution of edge dislocation used in the planar structure which enhances the device performance. Secondly, we optimize the size of replaced S/D SiGe stressor by commercial tool. Afterward we simulate the wrapped stressor and find the wrapped stressor with two advantages.
One is the etching process is less and the other is the strain field in the channel is higher than replaced stressor as the size optimization.
Subjects
3DIC
TSVs
strain
stress
FinFET
stressor
Type
thesis
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